DIL/NetPC DNP/9200: PIO Mapping

The DNP/9200 PIO bits PA0 to PA7, PB0 to PB7 and PC0 to PC3 are driven by the Atmel AT91RM9200 ARM9-based 32-bit microcontroller internal parallel input/output controller. This controller manages up 32 fully programmable input/output lines. 20 of these lines are used to implement the DNP/9200 20-bit PIO (Parallel Input Output Port). The bits of the DNP/9200 20-bit PIO are direct connected to signals of the Atmel AT91RM9200. The following table shows the mapping.

DNP/9200 PIO Mapping
Pin	Name	Function	AT91RM9200 PIO Signal
1	PA0	Parallel I/O, Port A, Bit 0	PIOB Controller Bit 6
2	PA1	Parallel I/O, Port A, Bit 1	PIOB Controller Bit 7
3	PA2	Parallel I/O, Port A, Bit 2	PIOB Controller Bit 8
4	PA3	Parallel I/O, Port A, Bit 3	PIOB Controller Bit 9
5	PA4	Parallel I/O, Port A, Bit 4	PIOB Controller Bit 10
6	PA5	Parallel I/O, Port A, Bit 5	PIOB Controller Bit 11
7	PA6	Parallel I/O, Port A, Bit 6	PIOC Controller Bit 1
8	PA7	Parallel I/O, Port A, Bit 7	PIOC Controller Bit 3
9	PB0	Parallel I/O, Port B, Bit 0	PIOA Controller Bit 27
10	PB1	Parallel I/O, Port B, Bit 1	PIOA Controller Bit 28
11	PB2	Parallel I/O, Port B, Bit 2	PIOA Controller Bit 29
12	PB3	Parallel I/O, Port B, Bit 3	PIOB Controller Bit 3
13	PB4	Parallel I/O, Port B, Bit 4	PIOB Controller Bit 4
14	PB5	Parallel I/O, Port B, Bit 5	PIOB Controller Bit 5
15	PB6	Parallel I/O, Port B, Bit 6	PIOA Controller Bit 5
16	PB7	Parallel I/O, Port B, Bit 7	PIOA Controller Bit 6
17	PC0	Parallel I/O, Port C, Bit 0	PIOA Controller Bit 1
18	PC1	Parallel I/O, Port C, Bit 1	PIOA Controller Bit 0
19	PC2	Parallel I/O, Port C, Bit 2	PIOA Controller Bit 2
20	PC3	Parallel I/O, Port C, Bit 3	PIOA Controller Bit 3

Please Note: Each AT92RM9200 parallel I/O pin is configurable, according to product definition as either a general-purpose I/O line only, or as an I/O line multiplexed with one or two peripheral I/Os. See also the DNP/9200 alternate function description.