DIL/NetPC ADNP/ESC1: 128-pin QIL Connector Pinout

The mechanical interface between the DIL/NetPC ADNP/ESC1 and existing devices and equipment is a 128-pin QIL (Quad- In- Line) connector with 2.54mm centers. This connector consist of four lines each with 32 pins.

128-pin QIL Connector Pinout (Part 1: Pins 1 - 64)
Pin	Name	Group	Function
1	PA0	PIO	Parallel I/O, Port A, Bit 0 (Driven by FPGA - see note)
2	PA1	PIO	Parallel I/O, Port A, Bit 1 (Driven by FPGA - see note)
3	PA2	PIO	Parallel I/O, Port A, Bit 2 (Driven by FPGA - see note)
4	PA3	PIO	Parallel I/O, Port A, Bit 3 (Driven by FPGA - see note)
5	PA4	PIO	Parallel I/O, Port A, Bit 4 (Driven by FPGA - see note)
6	PA5	PIO	Parallel I/O, Port A, Bit 5 (Driven by FPGA - see note)
7	PA6	PIO	Parallel I/O, Port A, Bit 6 (Driven by FPGA - see note)
8	PA7	PIO	Parallel I/O, Port A, Bit 7 (Driven by FPGA - see note)
9	PB0	PIO	Parallel I/O, Port B, Bit 0 (Driven by FPGA - see note)
10	PB1	PIO	Parallel I/O, Port B, Bit 1 (Driven by FPGA - see note)
11	PB2	PIO	Parallel I/O, Port B, Bit 2 (Driven by FPGA - see note)
12	PB3	PIO	Parallel I/O, Port B, Bit 3 (Driven by FPGA - see note)
13	PB4	PIO	Parallel I/O, Port B, Bit 4 (Driven by FPGA - see note)
14	PB5	PIO	Parallel I/O, Port B, Bit 5 (Driven by FPGA - see note)
15	PB6	PIO	Parallel I/O, Port B, Bit 6 (Driven by FPGA - see note)
16	PB7	PIO	Parallel I/O, Port B, Bit 7 (Driven by FPGA - see note)
17	PC0	PIO	Parallel I/O, Port C, Bit 0 (Driven by FPGA - see note)
18	PC1	PIO	Parallel I/O, Port C, Bit 1 (Driven by FPGA - see note)
19	PC2	PIO	Parallel I/O, Port C, Bit 2 (Driven by FPGA - see note)
20	PC3	PIO	Parallel I/O, Port C, Bit 3 (Driven by FPGA - see note)
21	RXD1	SIO	COM1 Serial Port, RXD Pin (Driven by FPGA - see note)
22	TXD1	SIO	COM1 Serial Port, TXD Pin (Driven by FPGA - see note)
23	CTS1	SIO	COM1 Serial Port, CTS Pin (Driven by FPGA - see note)
24	RTS1	SIO	COM1 Serial Port, RTS Pin (Driven by FPGA - see note)
25	DCD1	SIO	COM1 Serial Port, DCD Pin (Driven by FPGA - see note)
26	DSR1	SIO	COM1 Serial Port, DSR Pin (Driven by FPGA - see note)
27	DTR1	SIO	COM1 Serial Port, DTR Pin (Driven by FPGA - see note)
28	RI1	SIO	COM1 Serial Port, RI Pin (Driven by FPGA - see note)
29	RESIN	RESET	RESET Input
30	TX+	LAN	10/100 Mbps Ethernet Interface, TX+ Pin
31	TX-	LAN	10/100 Mbps Ethernet Interface, TX- Pin
32	GND	---	Ground
33	RX+	LAN	10/100 Mbps Ethernet Interface, RX+ Pin
34	RX-	LAN	10/100 Mbps Ethernet Interface, RX- Pin
35	RESOUT	RESET	RESET Output
36	VBAT	PSP (Product Specific Pins)	Real Time Clock Battery Input
37	CLKOUT	PSP (Product Specific Pins)	Clock Output (Default 3.6864 MHz)
38	TXD2	PSP (Product Specific Pins)	COM2 Serial Port, TXD Pin (Driven by FPGA - see note)
39	RXD2	PSP (Product Specific Pins)	COM2 Serial Port, RXD Pin (Driven by FPGA - see note)
40	INT5	PSP (Product Specific Pins)	Programmable Interrupt Input 5 (Driven by FPGA - see note)
41	INT4	PSP (Product Specific Pins)	Programmable Interrupt Input 4 (Driven by FPGA - see note)
42	INT3	PSP (Product Specific Pins)	Programmable Interrupt Input 3 (Driven by FPGA - see note)
43	INT2	PSP (Product Specific Pins)	Programmable Interrupt Input 2 (Driven by FPGA - see note)
44	INT1	PSP (Product Specific Pins)	Programmable Interrupt Input 1 (Driven by FPGA - see note)
45	CS4	PSP (Product Specific Pins)	Programmable Chip Select Output 4 (Driven by FPGA - see note)
46	CS3	PSP (Product Specific Pins)	Programmable Chip Select Output 3 (Driven by FPGA - see note)
47	CS2	PSP (Product Specific Pins)	Programmable Chip Select Output 2 (Driven by FPGA - see note)
48	CS1	PSP (Product Specific Pins)	Programmable Chip Select Output 1 (Driven by FPGA - see note)
49	IOCHRDY	PSP (Product Specific Pins)	I/O Channel Ready (Driven by FPGA - see note)
50	IOR	PSP (Product Specific Pins)	I/O Read Signal, I/O Expansion Bus (Driven by FPGA - see note)
51	IOW	PSP (Product Specific Pins)	I/O Write Signal, I/O Expansion Bus (Driven by FPGA - see note)
52	SA3	PSP (Product Specific Pins)	System Expansion Bus, Address Bit 3
53	SA2	PSP (Product Specific Pins)	System Expansion Bus, Address Bit 2
54	SA1	PSP (Product Specific Pins)	System Expansion Bus, Address Bit 1
55	SA0	PSP (Product Specific Pins)	System Expansion Bus, Address Bit 0
56	SD7	PSP (Product Specific Pins)	System Expansion Bus, Data Bit 7
57	SD6	PSP (Product Specific Pins)	System Expansion Bus, Data Bit 6
58	SD5	PSP (Product Specific Pins)	System Expansion Bus, Data Bit 5
59	SD4	PSP (Product Specific Pins)	System Expansion Bus, Data Bit 4
60	SD3	PSP (Product Specific Pins)	System Expansion Bus, Data Bit 3
61	SD2	PSP (Product Specific Pins)	System Expansion Bus, Data Bit 2
62	SD1	PSP (Product Specific Pins)	System Expansion Bus, Data Bit 1
63	SD0	PSP (Product Specific Pins)	System Expansion Bus, Data Bit 0
64	Vcc	---	3.3 Volt Power Input

128-pin QIL Connector Pinout (Part 2: Pins 65 - 128)
Pin	Name	Group	Function
65	SBHE	PSP (Product Specific Pins)	System Byte High Enable, System Expansion Bus (Driven by FPGA - see note)
66	IOCS16	PSP (Product Specific Pins)	I/O Chip Select 16, System Expansion Bus (Driven by FPGA - see note)
67	Reserved	PSP (Product Specific Pins)	Reserved.
68	Reserved	PSP (Product Specific Pins)	Reserved.
69	Reserved	PSP (Product Specific Pins)	Reserved.
70	BALE	PSP (Product Specific Pins)	Bus Latch Enable, System Expansion Bus (Driven by FPGA - see note)
71	AEN	PSP (Product Specific Pins)	Address Enable Signal, System Expansion Bus (Driven by FPGA - see note)
72	Reserved	PSP (Product Specific Pins)	Reserved. Don´t use
73	RCME	PSP (Product Specific Pins)	Remote Console Mode Enable
74	Reserved	PSP (Product Specific Pins)	Reserved. Don´t use
75	Reserved	PSP (Product Specific Pins)	Reserved. Don´t use
76	Reserved	PSP (Product Specific Pins)	Reserved. Don´t use
77	Reserved	PSP (Product Specific Pins)	Reserved. Don´t use
78	Reserved	PSP (Product Specific Pins)	Reserved. Don´t use
79	Reserved	PSP (Product Specific Pins)	Reserved. Don´t use
80	Reserved	PSP (Product Specific Pins)	Reserved. Don´t use
81	Reserved	PSP (Product Specific Pins)	Reserved. Don´t use
82	Reserved	PSP (Product Specific Pins)	Reserved. Don´t use
83	Reserved	PSP (Product Specific Pins)	Reserved. Don´t use
84	Reserved	PSP (Product Specific Pins)	Reserved. Don´t use
85	INT6	PSP (Product Specific Pins)	Programmable Interrupt Input 6 (Driven by FPGA - see note)
86	INT7	PSP (Product Specific Pins)	Programmable Interrupt Input 7 (Driven by FPGA - see note)
87	IDERES	PSP (Product Specific Pins)	IDE Interface Reset Output (Driven by FPGA - see note)
88	IDECS0	PSP (Product Specific Pins)	IDE Interface Chip Select 0 (Driven by FPGA - see note)
89	IDECS1	PSP (Product Specific Pins)	IDE Interface Chip Select 1 (Driven by FPGA - see note)
90	Reserved	PSP (Product Specific Pins)	Reserved. Don´t use
91	Reserved	PSP (Product Specific Pins)	Reserved. Don´t use
92	Reserved	PSP (Product Specific Pins)	Reserved. Don´t use
93	Reserved	PSP (Product Specific Pins)	Reserved. Don´t use
94	Reserved	PSP (Product Specific Pins)	Reserved. Don´t use
95	Reserved	PSP (Product Specific Pins)	Reserved. Don´t use
96	GND	---	Ground
97	LANLED	PSP (Product Specific Pins)	LAN Interface Activity LED
98	Reserved	PSP (Product Specific Pins)	Reserved. Don´t use
99	RSTDRV	PSP (Product Specific Pins)	Reset Output, System Expansion Bus (Driven by FPGA - see note)
100	SA23	PSP (Product Specific Pins)	System Expansion Bus, Address Bit 23
101	SA22	PSP (Product Specific Pins)	System Expansion Bus, Address Bit 22
102	SA21	PSP (Product Specific Pins)	System Expansion Bus, Address Bit 21
103	SA20	PSP (Product Specific Pins)	System Expansion Bus, Address Bit 20
104	SA19	PSP (Product Specific Pins)	System Expansion Bus, Address Bit 19
105	SA18	PSP (Product Specific Pins)	System Expansion Bus, Address Bit 18
106	SA17	PSP (Product Specific Pins)	System Expansion Bus, Address Bit 17
107	SA16	PSP (Product Specific Pins)	System Expansion Bus, Address Bit 16
108	SA15	PSP (Product Specific Pins)	System Expansion Bus, Address Bit 15
109	SA14	PSP (Product Specific Pins)	System Expansion Bus, Address Bit 14
110	SA13	PSP (Product Specific Pins)	System Expansion Bus, Address Bit 13
111	SA12	PSP (Product Specific Pins)	System Expansion Bus, Address Bit 12
112	SA11	PSP (Product Specific Pins)	System Expansion Bus, Address Bit 11
113	SA10	PSP (Product Specific Pins)	System Expansion Bus, Address Bit 10
114	SA9	PSP (Product Specific Pins)	System Expansion Bus, Address Bit 9
115	SA8	PSP (Product Specific Pins)	System Expansion Bus, Address Bit 8
116	SA7	PSP (Product Specific Pins)	System Expansion Bus, Address Bit 7
117	SA6	PSP (Product Specific Pins)	System Expansion Bus, Address Bit 6
118	SA5	PSP (Product Specific Pins)	System Expansion Bus, Address Bit 5
119	SA4	PSP (Product Specific Pins)	System Expansion Bus, Address Bit 4
120	SD15	PSP (Product Specific Pins)	System Expansion Bus, Data Bit 15
121	SD14	PSP (Product Specific Pins)	System Expansion Bus, Data Bit 14
122	SD13	PSP (Product Specific Pins)	System Expansion Bus, Data Bit 13
123	SD12	PSP (Product Specific Pins)	System Expansion Bus, Data Bit 12
124	SD11	PSP (Product Specific Pins)	System Expansion Bus, Data Bit 11
125	SD10	PSP (Product Specific Pins)	System Expansion Bus, Data Bit 10
126	SD9	PSP (Product Specific Pins)	System Expansion Bus, Data Bit 9
127	SD8	PSP (Product Specific Pins)	System Expansion Bus, Data Bit 8
128	Vcc	---	3.3 Volt Power Input

Please note: These pins are driven by a Altera EP1C6F256 Cyclone FPGA. It is possible to change the function of these pins. Please contact our support staff for more details.